Dependency on the Makefile

by Paul Hsieh

For people who have not been duped into surrendering control of their programming projects to GUI based snake oil, authoring makefiles is a necessity. As projects become bigger its also usually inevitable that using some sort of automated make-depend rule generator is required. So as long as you know the source files its usually a breeze to compile. (WATCOM C/C++'s makefile system does not require an additional make-depend tool, since it supports the .AUTODEPEND directive.)

The one problem that is typically encountered, however, is that your sources are dependent on the definition of macros that are defined in the makefile. So if you change the macro in the makefile, you have to either completely remake or hand select the modules that are dependent on the macro change for remaking. Both options defeat the main purpose of what the makefile is trying to solve.

So the question is now put to us -- how does one make source make rules dependent on the makefile?

Well for C sources, fortunately there is a clever hack that will allow you to include the makefile as part of the source file in a non-intrusive way. (Which is all that is required for an automated make-depend tool to generate the dependency.)

The standard convention for makefile comments is to use a "#" character at the beginning of a comment line. Furthermore one way to skip over C code from compilation is to surround it in a "#if 0"/"#endif" pair. Thus it remains to put "#if 0" as the first line of the makefile, and "#endif" as the last line of the makefile, then include the makefile in the C source. Then you can leave it to your make-depend tools to make sure that a given C source rule includes a dependency to the makefile.

Simple enough wouldn't you say? Unfortunately, this hack is C specific -- I don't know of any way to do something similar for assembly or other languages.