The Cyrix
Jalapeno presentation at Microprocessor forum
UPDATE: As of 05/05/99, National Semiconductor has announced that they
will not be continuing PC processor development. However on 06/31/99, after
I and others had pretty much written off Cyrix, VIA signed a letter of intent
indicating they would purchase Cyrix. It is likely Cyrix may lose some of
their engineers, and their schedules may slip a bit.
Cyrix has claimed that the processor will be available in Q4'99 at more than
600Mhz in a 0.18 micron process, with an on chip 3D accelerator, and
supporting memory bandwidth's up to 3.2 GB/s.
The presentation they give above says something that doesn't make any sense
to me: 3-issue buys little performance because applications are limited by
OS performance. First of all, I dispute the applications are limited by OS
performance (they may be limited by device or memory performance, but the OS,
no matter how badly written, should not factor in as a performance
consideration of any reasonably written application.) Secondly, Cyrix did not
explain how they arrived at 3-issue data especially since they don't make a
3-decode processor -- they could just be taking P-II data which is not
representative of the K7's or even RISE's mP6 decode rate.
The 6x86MX
- 1 FPU non-pipelined (slow, but asynchronous)
- 2 Load or Stores in EX units
- Native x86 execution => 2 entry out-of-order window.
- L2 cache on motherboard -- direct mapped
- 64KB L1 cache unified
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Jalapeno
- 2 FPUs fully pipelined
- 1 Load/Store unit
- Translation to "nodes" => 16x6 entry out-of-order window.
- 256KB L2 cache on chip -- 8-way set associative. pipelined to core
frequency
- 32KB L1 cache harvard architecure (16K I-cache, 16K D-cache) non-blocking
pending miss mechanism
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It is clear that Cyrix has made some compromises in moving from the 6x86MX
to the Jalapeno core. However, they have clearly identified areas where they
have had problems in the 6x86MX. The on chip L2 cache will probably help
memory bandwidth more than halving and de-unifying the L1 cache will hurt.
But going with a single load/store unit seems like too much of a compromise
to me. The superscalar pipelined FPUs will easily pull them ahead of the
P-II's floating point performance, and it will probably be not too far off
of the K7's performance. But for ordinary performance, my rough gut feel is
that this processor will perform roughly like a K6 with significantly higher
memory bandwidth (possibly like a K6-3 at a high clock rate.)
But the real differentiator of Jalapeno from other x86 CPUs is that like the
MediaGX, it includes a graphics core. The 256K on chip L2 cache is shared for
texture caching as well as ordinary CPU caching. On the face of this, the
problem is that the bandwidth rates and content of the CPU and graphics
processor are entirely different, and therefore such an idea would tend have
the two thrash each other. But Cyrix has solved that problem by partitioning
the L2 cache into graphics and non-graphics sections (by allowing only one of
the "ways" of the cache to be dedicated for graphics.) So the value add of
the graphics core will not be from an integration stand point of view, but
rather from a core frequency and (possibly) memory bandwidth advantage.
On the one hand, including a graphics core on chip may prove to be the
greatest value add (in terms of total system cost.) But on the other, they
are pissing off all the graphics vendors, who are intensely competitive, and
will be highly motivated to outperforming the Cyrix core. I don't have any
reason to believe that Cyrix has graphics designers that can compete with
nVidia, 3DFX, ATI, Matrox, or even S3 (all of whom have experts previously
employed at SGI, or other workstation graphics companies.) On the flip side,
Cyrix already has experience with MediaGX, and so should have a reasonable
idea about where they went wrong with it in terms of a performance target
(MediaGX, although not a complete failure did not quite deliver on its promise
in terms of its potential market.)
I have a hunch that Cyrix may have bought a deferred rendering graphics core
from GigaPixel or Stellar graphics -- the bullet points that they include
suggest that they are avoiding the term "edge anti-aliasing" and specifying
the minimum they need to that is both true and non-revealing. They also spent
no time describing the kind of technology that the graphics core is comprised
of which leads me to believe they may not understand it too well themselves.
This is a total guess though.
Like the K7, Jalapeno will also need a new motherboard to accomodate their
complete interated system concept. But they have already done it once with
MediaGX, and thus should have some good knowledge on how to do this already.
600Mhz+ in Q4'99 is sounding reasonable but not earth shattering to me. Like
I commented about AMD above, crucial to the success will be delivering clock
rates that are competitive with what Intel will be offering. Intel's roadmap
suggests that they will be shipping well above 600Mhz by this time frame.
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